Digital clock frequency multiplier
US6008676A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention describes a circuit and method for creating a double clock frequency. The circuit uses a sequence of delay elements to delay the primary clock. A delay detector determines when a delayed clock is out of phase with the primary clock. A delay is selected that is one half the delay producing the out of phase delayed clock. The selected delay is used to combine with the primary clock to produce a double clock frequency. Control signals for selecting the "half" delayed clock are latched to prevent clock jitter and spurious signal from producing error signals in the double frequency clock. Different duty cycles can be established by varying the selected delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.