Asynchronously programmable frequency divider circuit with a symmetrical output
US6009139A · kind A · utility
17Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1998 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Jun 19, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/66
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A programmable divider circuit having an adjustable shift register is coupled to a clock and to an output. The shift register receives a clock signal having a clock signal frequency and outputs an output signal with an output frequency corresponding to a user selected divide ratio of the clock signal frequency. Control inputs are coupled to the adjustable shift register to receive control data for adjusting a length of the shift register, the length of the shift register corresponding to the user selected divide ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.