Dual processor audio decoder and methods with sustained data pipelining during error conditions
US6009389A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1997 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Nov 14, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L19/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of concealing errors received in a stream of data by a multiprocessor system having a first digital signal processor for initial processing of incoming data and a second digital signal processor for processing data passed from the first processor. The method includes the steps of detecting an error in an incoming frame of the stream of data with the first processor, sending an error message from the first to the second processor, halting transmission of the remainder of the frame to the second processor, and processing a frame of dummy data with the second processor. The frame of dummy data is passed to a processing engine forming a portion of the second processor to maintain data pipelining. Interprocessor communications between the first and second processors is established by handshaking through an interprocessor communications register, wherein the first processor detects an error in a frame of data and sends a message to the second processor. In selected embodiments, the first and second processors are fabricated on a single integrated circuit chip along with shared memory for exchanging data between the processors and data memory associated with each processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.