Finite field inverse circuit
US6009450A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Dec 24, 1997 |
| Grant date | Dec 28, 1999 |
| Priority date | — |
| Expiry date | Dec 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/726
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A finite field inverse circuit has a finite field data unit (1112) and an inverse control unit (1110). The inverse control unit includes (1110) a k.sub.l and k.sub.u decrementer pair (1108, 1122), a k.sub.l -k.sub.u difference unit (1106), an inverse control finite state machine (1102), and a one-bit memory (1104) coupled to the inverse control finite state machine (1102). The finite field data unit (1112) includes four m bit wide registers that are shift registers designated as B (1120), A (1118), M (1114), and C (1116), where B- is a first register, A- is a second register, M- is a irreducible polynomial register, and C- is a field element register. An the irreducible polynomial is loaded left justified in the M-register, a field element to be inverted is loaded left justified in the C-register, and a single "1" is loaded in an LSB bit of the B-register. The field element is then inverted in 2n+2 system clock cycles where n is a field size associated with the field element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.