Method of making dual-gate CMOSFET

US6010925A · kind A · utility

Assignee

• Utek Semiconductor Corp. · TW

Inventor

• Shou-Wei Hsieh · Hsinchu, TW

Key dates

• Filing date: Mar 2, 1998
• Grant date: Jan 4, 2000
• Expiry date: Mar 2, 2018

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/857

Abstract

A method of making dual-gate structure with only three masking steps is provided. The process comprising: forming well and isolation region to define PMOS and NMOS regions on a semiconductor substrate; forming a conformal layer of PMOS gate oxide by thermal oxidation; providing a conformal layer of P type conducting material overall; removing portions of the P type material and PMOS gate oxide on the NMOS region with the aid of the first patterned mask; forming a conformal layer of NMOS gate oxide by thermal oxidation; providing a conformal layer of N type conducting material overall; forming the NMOS gate structure with the aid of the second patterned mask; performing ion implantation; providing a conformal layer of oxide overall, then etching into NMOS spacers; performing ion implantation; providing a conformal layer of protecting dielectric layer overall; proving the third patterned mask to remove portions of the protecting dielectric layer, the NMOS gate oxide, P type conducting layer and PMOS gate oxide to form the PMOS gate structure, thereby leaving a protecting dielectric layer over the NMOS region; performing ion implantation; providing a conformal layer of oxide overall, …