Reduction of dislocations in a heteroepitaxial semiconductor structure
US6010937A · kind A · utility
446Cited by
39References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 1995 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Sep 5, 2015 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02E10/547
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A heteroepitaxial semiconductor device having reduced density of threading dislocations and a process for forming such a device. According to one embodiment, the device includes a substrate which is heat treated to a temperature in excess of 1000.degree. C., a film of arsenic formed on the substrate at a temperature between 800.degree. C. and 840.degree. C., a GaAs nucleation layer of less than 200 angstroms and formed at a temperature between about 350.degree. C. and 450.degree. C., and a plurality of stacked groups of layers of InP, wherein adjacent InP layers are formed at different temperatures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.