CMOS offset trimming circuit and offset generation circuit
US6011425A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1997 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Jul 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CMOS offset trimming circuit and offset generation circuit for obtaining the corrected optimum offset value for correcting the offset generated in the CMOS analog circuit. An offset trimming circuit comprises a flip-flop for loading a data to be used for obtaining an optimum offset value or a data to be trimmed according to an input clock, a fuse circuit for setting the circuit with a corrected optimum offset value obtained in a corresponding mode by receiving the data loaded on the flip-flop and the mode selection signal as an input signal, and a selection logic circuit for outputting a selected signal as a trimming output signal by selecting one from the group consisting of the data loaded on the flip-flop and the data output from the fuse circuit according to the operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.