Transmission-line loss equalizing circuit
US6011435A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 1997 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Jan 6, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transmission-line loss equalizing circuit includes an equalizer, a gain control circuit for controlling the gain of the equalizer based upon the peak value of an equalized output, a slicer for slicing the equalized output and outputting a data pulse, a timing extraction pulse and an equalization control pulse, a DC feedback level detector for detecting a DC component of the equalized output and feeding the DC component back to the equalizer, and an attenuating circuit provided as an initial stage of the equalizer. A plurality of .sqroot.fAGC circuits constructing the equalizer are cascade-connected and constructed by a differential non-inverting amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.