Fuseless memory repair system and method of operation
US6011734A · kind A · utility
112Cited by
6References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 12, 1998 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Mar 12, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Built-In Self Test (720) generates a BIST FAIL signal when a failure is detected at a specific address within a memory array (110). The address associated with the failure is stored in a latch (210). During normal operation, the address stored in latch (210) is compared to addresses being currently accesses. A HIT signal is generated when a match occurs. The HIT signal disables selection of the defective row in array (110). A redundant row select signal selects the redundant row (112) to replace the defective row.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.