Video capture device with adjustable frame rate based on available bus bandwidth
US6012109A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 9, 1997 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Sep 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An image acquisition apparatus, for acquiring frames of a video signal and storing these frames in a computer memory, is disclosed. An analog video input signal, comprising a sequence of video frames, is digitized by an A/D converter. The resulting digitized frames are selectively gated into a frame acquisition buffer. The frame acquisition buffer includes two or more memory segments, each configured to store a digitized video frame. A DMA controller transfers video frames from the frame acquisition buffer to the computer memory via a peripheral bus. Frame acquisition control logic (e.g. a second DMA controller) selects which video frames of the frame sequence are to be acquired into the frame acquisition buffer. The frame acquisition control logic and the DMA controller are coordinated by a status memory which contains a status flag for each memory segment. The frame acquisition control logic: checks a status flag to ensure that the corresponding memory segment is available before commanding the memory segment to be overvritten with a new video frame; and changes the status flag to indicate unavailability. The DMA controller updates a status flag to indicate availability when it f…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.