Computer having multiple address ports, each having logical address translation with base and limit memory management
US6012135A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1994 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Dec 1, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for a logical address translator which translates a logical address into a physical address in a computer. The computer includes a plurality of address ports. Each address port includes a logical address translator, which includes a plurality of segment-register sets. Each segment-register set holds values which specify address boundaries and translation mapping of a corresponding logical segment. A segment detector is coupled to the plurality of segment-register sets, wherein the segment detector operates to determine whether the logical address is within the specified address boundaries of the logical segment. An address mapper is coupled to the plurality of segment-register sets, wherein the address mapper operates to translate the logical address into a physical address. A translation controller is connected to the segment detector and the address translator, wherein the translation controller operates to output the physical address if the segment detector determines that the logical address is within the specified address boundaries of the logical segment. One embodiment of the segment-register set includes a base address, a limit address, and a physical m…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.