System for verifying the effectiveness of a RAM BIST controller's ability to detect faults in a RAM memory using states indicating by fault severity information
US6012157A · kind A · utility
13Cited by
11References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 3, 1997 |
| Grant date | Jan 4, 2000 |
| Priority date | — |
| Expiry date | Dec 3, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing a RAM BIST controller by initializing a RAM behavior model with known fault data, running a RAM BIST controller model along with the RAM behavior model, and then comparing the output of the RAM BIST controller model with the known fault data to determine if there are any differences. A difference will indicate a fault in the RAM behavior model. The accuracy of the RAM BIST controller can then be used to compare the design of the RAM BIST controller with designs for other RAM BIST controllers in order to find the ideal RAM BIST controller for the intended purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.