Synchronous semiconductor memory device having internal circuitry enabled only when commands are applied in normal sequence
US6014340A · kind A · utility
13Cited by
6References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a synchronous semiconductor memory device in which contents of an internal operation is designated by commands applied in synchronization with a clock signal, operations of decoding read, write and precharge commands different from an active command for activating the internal operation are enabled only when the active command is active. Even if a command such as read command other than the active command is applied during an inactive state of internal circuits, other command decoder cannot perform the decoding, so that unnecessary circuit operation can be prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.