Method for performing timing analysis of a clock circuit
US6014510A · kind A · utility
31Cited by
21References
27Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 27, 1996 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | Nov 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for accurately and precisely computing the output signal transition times in a clock distribution, or buffering, network of a data processing system is provided herein. This methodology may be implemented in transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. Furthermore, the static timing analysis techniques traditionally implemented are modified to more accurately compute signal delays and transition times at the outputs of a clock distribution network circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.