Processor with accelerated array access bounds checking
US6014723A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 23, 1997 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | Jan 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/451
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An array boundary checking apparatus is configured to verify that a referenced element of an information array is within a maximum array size boundary value and a minimum array size boundary value. The array boundary checking apparatus of the invention includes an associative memory element that stores and retrieves a plurality of array bound values. Each one of the plurality of array bound values is associated with one of the plurality of array access instructions. An input section simultaneously compares the array access instruction identifier with at least a portion of each of the stored array reference entries, wherein the array access instruction identifier identifies an array access instruction. An output section is configured to provide as an array bounds output values one of the plurality of array bound values stored in one of the plurality of memory locations of the associated memory element. A first comparison element compares the value of the referenced element and the maximum array index boundary value and provides a maximum violation signal if the value of the element is greater than the maximum array size boundary value. A second comparison element compares the value …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.