Method and apparatus for maintaining cache coherency in an integrated circuit operating in a low power state
US6014751A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 1997 |
| Grant date | Jan 11, 2000 |
| Priority date | — |
| Expiry date | May 5, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.