High availability error self-recovering shared cache for multiprocessor systems

US6014756A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gerhard Dottling · Waldenbuch, DE
• Klaus J. Getzlaff · Schenefeld, DE
• Bernd Leppla · Meiningen, DE
• Wille Udo · Holzgerlingen, DE

Key dates

• Filing date: Dec 16, 1996
• Grant date: Jan 11, 2000
• Expiry date: Dec 16, 2016

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/141
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A high availability shared cache memory in a tightly coupled multiprocessor system provides an error self-recovery mechanism for errors in the associated cache directory or the shared cache itself. After an error in a congruence class of the cache is indicated by an error status register, self-recovery is accomplished by invalidating all the entries in the shared cache directory means of the accessed congruence class by resetting Valid bits to "0" and by setting the Parity bit to a correct value, wherein the request for data to the main memory is not cancelled. Multiple bit failures in the cached data are recovered by setting the Valid bit in the matching column to "0". The processor reissues the request for data, which is loaded into the processor's private cache and the shared cache as well. Further requests to this data by other processors are served by the shared cache.