Vertical field effect transistor and manufacturing method thereof
US6015725A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 19, 1997 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Aug 19, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) is formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of recess (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.