Methods of fabricating integrated circuit memory devices including silicide blocking layers on memory cell transistor source and drain regions

US6015748A · kind A · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Hong Ki Kim · Daegu, KR
• Duck-Hyung Lee · Seojong-myeon, KR
• Chang-Sik Choi · Seojong-myeon, KR

Key dates

• Filing date: May 4, 1999
• Grant date: Jan 18, 2000
• Expiry date: May 4, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/50

Abstract

Integrated circuit memory devices are fabricated by fabricating an array of memory cell field effect transistors and peripheral circuit field effect transistors that are spaced-apart from the memory cell transistors, in an integrated circuit substrate. The memory cell transistors include spaced-apart memory cell transistor source and drain regions and a memory cell gate therebetween. The peripheral circuit transistors include spaced-apart peripheral circuit transistor source and drain regions and a peripheral circuit gate therebetween. A silicide blocking layer is formed on the memory cell transistor source and drain regions. The integrated circuit substrate is silicided to thereby form a silicide layer on the memory cell transistor gates, on the peripheral circuit source and drain regions and on the peripheral circuit gates, such that the memory cell transistor source and drain regions are free of the silicide layer thereon. Accordingly, low contact resistance silicide regions may be selectively provided in memory cells without degrading the leakage characteristics thereof.