Stacked silicon-controlled rectifier having a low voltage trigger and adjustable holding voltage for ESD protection

US6016002A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Julian Zhiliang Chen · Dallas, US
• Thomas A. Vrotsos · Richardson, US
• Wayne T. Chen · Plano, US

Key dates

• Filing date: Dec 18, 1997
• Grant date: Jan 18, 2000
• Expiry date: Dec 18, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002

Abstract

An SCR (68) for protecting an integrated circuit (62) against ESD events is provided having a trigger voltage which is automatically adjusted to different trigger voltage levels in response to power being applied to the integrated circuit (62). An enhancement-type P-channel transistor (78) is provided for determining the trigger voltage. When operating power is not being applied to the integrated circuit (62), the P-channel transistor (78) threshold voltage determines the voltage at which the SCR (68) is triggered. When operating power is being applied to the integrated circuit (62), the operating voltage is applied to the gate of the P-channel transistor (78), and then the operating voltage and the threshold voltage for the P-channel transistor (78) determine the trigger voltage of the SCR (68). Then, a PNP and NPN transistor pair (76, 80) that form the SCR (68) are latched to shunt the protected signal path (69) to ground. The SCR (68) remains latched until the voltage applied to the signal path (69) falls beneath a holding voltage of the SCR (68). A plurality of the SCRs (126, 128) may be connected in series, such that the overall holding voltage for the series of SCRs (126, 128…