Power on reset circuit capable of generating power on reset signal without fail
US6016068A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 6, 1998 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Mar 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/223
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power on reset circuit includes: interconnected first and second inverter circuits; a capacitor connected to an input node of the first inverter circuit; and a buffer circuit responsive to voltage at an output node for generating a power on reset signal. In the power on reset circuit, in order to increase source voltage of an N channel MOS transistor in the second inverter circuit to a voltage higher than ground voltage, a diode-connected transistor is inserted between the source of the transistor and a ground node. Thus, the power on reset circuit never fails to produce the power on reset signal even when power supply voltage is dropped.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.