Fuse-latch circuit having high integration density
US6016265A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1998 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Dec 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor IC apparatus including a fuse-latch unit. The fuse-latch unit comprises many fuses and latch output circuits. The fuses and the latch output circuits are arranged at pitches as short as possible, leaving virtually no dead spaces between them. The fuse-latch unit is therefore short in the direction the fuses and latch output circuits are arranged, thus occupying only a small area. The latch output circuits are arranged in two parallel columns. The fuses are arranged in one column extending between the two columns of latch output circuits. The fuses are connected, alternately to the latch output circuits of the first column and those of the second column.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.