Flash memory wear leveling system and method
US6016275A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 4, 1998 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Nov 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A wear leveling system and method of a flash memory cell uses the amount of time required to perform an erasing operation on a sector of the flash memory to determine whether the memory cells in the sector have degraded to an unacceptable level. The actual time required to erase a sector of a flash memory array is compared to a reference erasing time required to erase a unit sector under the state of the worst allowable degradation. If the actual erasing time of a sector exceeds the reference erasing time, logical addresses corresponding to the sector are re-mapped to the physical addresses of a different sector. On the other hand, when the actual erasing time is shorter than or equal to the reference erasing time, a controller continues to use the unit sector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.