Memory with word line voltage control
US6016281A · kind A · utility
24Cited by
1References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 17, 1997 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Dec 17, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory array, decoding circuitry for selectively applying a turn-off voltage to selected word lines of the memory array for turning off conduction in the main conduction paths of the transistors whose gate electrodes are connected to the selected word lines and for selectively applying an increased turn-off voltage to selected word lines. The application of different values of turn-off voltage may be used to test the susceptibility of the memory array to gate induced drain leakage (GIDL) and to determine an optimum range of turn-off voltages to be applied to the word lines for operation with reduced leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.