Apparatus for an automatic speed and data length selection of an asychronous data link
US6016309A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1996 |
| Grant date | Jan 18, 2000 |
| Priority date | — |
| Expiry date | Nov 19, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0262
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
To establish the communication between two devices connected through an asynchronous data link, an adapter for automatically identifies configuration parameters. The configuration parameters may be the transmission speed, the data bits length (seven or eight), the parity (odd or even) if existing and the number of stop bits (one or two). Thus, there are six combinations of the four parameters. Each one of the configuration is detected by an adapter which is independent from the others. It comprises a control circuit (170) receiving deserialized data bits signal (RXD) from a connector (120), a clock generator (160) for generating clock signals and varying the clock frequency so as to adapt to asynchronous data transmission speed, a timer (220) for synchronizing the number of data bytes so as to adapt to the data bit length and counters for counting the number of times a predetermined configuration matches. A parity checker may be also implemented in case a parity bit is used in the data transmission. The six adapters may be connected in parallel by the RXD signal so that each adapter operates simultaneously so that each counter may inform first the microcontroller of the configurati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.