Error correction device
US6017146A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 1996 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | May 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04H2201/13
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A demodulating circuit demodulates a received signal, and outputs patterns of demodulated data and reliability information bits indicating correctness of the demodulated data. These are supplied to first and second shift registers (4 and 5), respectively. When the number of reliability information bits of Level 1 in the second shift register is a predetermined value or less, a shift operation is repeated a plurality of times. When a reliability information bit of Level 1 is outputted, an error correction control circuit (7) successively outputs all possible bit patterns of the demodulated data An EXOR gate (10) generates all possible patterns of demodulated data An error correcting circuit (11) carries out error correction for all the patterns. When the number is larger than the predetermined value, the error correction is carried out only for the demodulated data supplied from the demodulating circuit in a conventional manner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.