Distributed block redundancy for memory devices
US6018483A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1998 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Dec 10, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory bank, in accordance with the present invention includes a plurality of memory sub-units, each memory sub-unit being divided by sense amplifier banks wherein adjacent memory sub-units share the sense amplifier bank therebetween. Redundancy regions are also included which are disposed in the memory sub-units and sharing circuitry therewith. The redundancy regions are located at a first end portion and a second end portion of the memory bank, the first and second end portions being disposed at opposing ends of the memory bank. A central sense amplifier bank is disposed between a first half and a second half of the memory bank wherein failed devices in the first half of the memory bank are replaced by a device in the redundancy region at the first end portion and failed devices in the second half of the memory bank are replaced by a device in the redundancy region at the second end portion such that sense amplifier contention is prevented for the central sense amplifier bank. Also, a method for replacing failed devices is disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.