Semiconductor memory device with cascaded burn-in test capability
US6018485A · kind A · utility
3Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1998 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Dec 28, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device with a cascaded burn-in test capability for a plurality of memory cell blocks. A delayed feedback signal is communicated between memory cell block selection circuits to create the cascade burn-in.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.