Method for reducing circuit area by grouping compatible storage devices
US6018622A · kind A · utility
8Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 1997 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Sep 24, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a control block design methodology, a control block is designed, synthesized, and laid out. The control block includes one or more storage devices, such as flops. The flops include a header which buffers signals common to the flops and a storage cell for storing data. A flop grouping tool is used to merge flops having the same type of header into a flop having storage equivalent to the merged flops but using a single header. Multiple instances of the header may be deleted from the control block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.