Disk array controller for reading/writing striped data using a single address counter for synchronously transferring data between data ports and buffer memory
US6018778A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 3, 1996 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | May 3, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2211/1054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disk drive array controller and method carries out disk drive data transfers not only concurrently but also synchronously with respect to all of the drives in the array. For synchronous operation, only a single-channel DMA is required to manage the buffer memory. A single, common strobe is coupled to all of the drives for synchronous read and write operations, thereby reducing controller complexity and pin count. A ring-structure drive data bus together with double suffering techniques allows use of a single, common shift clock instead of a series of staggered strobes a required in prior art for multiplexing/demultiplexing buffer memory data, again providing for reduced controller complexity and pin count in a preferred integrated circuit embodiment of the new disk array controller. Methods and circuitry also are disclosed for generating and storing redundant data (e.g. "check" or parity date) "on the fly" during a write operation to a RAID array. Techniques also are disclosed for reconstructing and inserting missing data into a read data stream "on the fly" so that a disk drive failure is transparent to the host.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.