Integrated relay ladder language, reduced instruction set computer
US6018797A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 9, 1997 |
| Grant date | Jan 25, 2000 |
| Priority date | — |
| Expiry date | Dec 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/15127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated RISC and relay ladder logic processor uses shared registers, program counter, bus lines, and processing circuitry to eliminate delays associated with transfer of control in co-processor type architecture. The RISC instructions do not significantly interfere with the specialized hardware needed for rapid relay logic execution, the latter which may be further improved through the use of a pipeline well suited for relay ladder logic which creates few pipeline hazards. Two levels of condition codes are used for the arithmetic and logic instructions to permit nested arithmetic operations without interference with those instructions visible to the user. Hybrid instructions are provided to synchronize the relay ladder instructions with the arithmetic instructions, thus truly integrating the two instruction sets.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.