Intergrated circuit die assembly
US6020646A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Dec 5, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) die carrier assembly includes a thinned IC die mounted to a substrate or carrier. The IC die is mounted to the carrier via a thin layer of glass. The carrier facilitates fixturing and provides support during the lapping process used to thin the die. Ball bonding, wire bonding, thin film or thick film conductors can be used to interconnect the pads on the IC die to the pads on the carrier. The coefficients of the thermal expansion of the IC die and the carrier are closely matched to avoid damage to the IC die due to uneven expansion of the thinned IC die relative to the carrier. The IC die carrier assembly is better suited for ultrahigh vacuum and high temperature environments than conventional IC die carrier assemblies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.