CMOS low-voltage comparator
US6020768A · kind A · utility
36Cited by
19References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 13, 1998 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | May 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/2481
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A comparator circuit providing for improved symmetry of operation. The circuit includes two delay paths to facilitate rising and falling input transitions. Such paths are made up of an equal number and type of current mirrors. The circuit also includes an input differential pair wherein both delay paths are coupled to a single transistor of the pair.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.