Transparent latch-based sequencer and sequence controlling method
US6020770A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 1998 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | May 6, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sequence-controlled digital circuit (21) is presented. The circuit (21) includes a divider (55) and a plurality of transparent latches (51-54) which together form a latch-based sequencer (42). Typically, a clock signal (43) is divided by the divider (55) into an inverted half-clock signal (45) and a non-inverted half-clock signal (44), each enabling alternate latches (51-54) arranged in a cascade. In the cascade, an output of each latch (51-54) drives an input of the following latch (51-54), one such being an inverting output and the rest non-inverting outputs, to form a twisted-loop counter (50). Each output of each latch (51-54) drives a clock input of a flip-flop (61-68), with a serial input signal (46) driving all data inputs, to form a temporal-to-spacial converter (40). Only the divider (55) operates at the rate of the clock signal (43).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.