Sigma-delta analogue-to-digital conversion circuits
US6020836A · kind A · utility
9Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 24, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Jun 24, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/454
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A third-order sigma-delta analogue-to-digital conversion circuit has a filter comprising the cascaded arrangement of three individual filter circuits, a quantization circuit and a monitoring circuit. The monitoring circuit detects for a predetermined, periodic pattern in the output bit stream. The periodicity of this pattern is ##EQU1## when f.sub.c is the converter sampling frequency and f.sub.r is the resonant frequency of the filter. If the pattern is detected, the monitoring circuit resets the filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.