Method and apparatus for precharging bitlines in a nonvolatile memory
US6021072A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 1998 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Jul 27, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for precharging a selected bitline (20) in a nonvolatile memory array using a boost circuit (54) in parallel to a pull-up device (22) for biasing the bitline. The boost circuit (54) is controlled by a pulse signal (26). One embodiment uses a regulator circuit (56) to isolate the boost circuit (54) from the bitline when the bitline voltage exceeds a threshold voltage level. The regulator triggers a delay circuit (58) which is coupled to a sense amplifier (60). The delay circuit (58) then defers activation of the sense amplifier (60) until the voltage on the selected bitline (20) is below a sense amplifier threshold voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.