Video FIFO overflow control method that blocks video encoder data when overflow is imminent and resumes flow when frames sizes have returned to nominal size
US6021449A · kind A · utility
17Cited by
8References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 1, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Aug 1, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/242
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multimedia terminal having a host processor, an audio and video encoder and a system time clock. The encoders are input as digital video elementary frames into a multiplexer. The multiplexer includes a mux processor, a video FIFO and a video mux logic circuit coupled to both the mux processor and the video FIFO. Mux logic is operative to monitor video FIFO fullness and to signal the mux processor when there is sufficient video data in the FIFO to form the payload of a transport packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.