Combining plural data lines and clock lines into set of parallel lines and set of serial lines
US6021450A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | Sep 4, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4273
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data transfer system includes a plurality of functional blocks each provided with a function module for controlling data transfer between memories of the plurality of functional blocks, by being connected to a function module of other functional blocks via n sets of data signal lines and clock signal lines so that the data transfer proceeds in a synchronized manner. Each of the n sets of data signal lines and clock signal lines is appropriately combined with one another depending on a required condition for communicating with destination functional blocks, such that a plurality of sets of data signal lines and clock signal lines are used for parallel transfer and a single set of a data signal line and a clock signal line is used for serial transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.