Processor with sleep and deep sleep modes
US6021500A · kind A · utility
68Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 7, 1997 |
| Grant date | Feb 1, 2000 |
| Priority date | — |
| Expiry date | May 7, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/3203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor has a clock generator circuit, a sleep pin that receives an external sleep signal, and a first interface circuit coupled to the clock generator circuit and the sleep pin. The clock generator circuit generates a core clock signal and a bus clock signal in response to an external clock signal. When the external sleep signal is asserted, the processor enters a sleep state when the core clock signal and the bus clock signal are in a first predetermined relationship with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.