Process for manufacturing solder leads on a semiconductor device package
US6022758A · kind A · utility
137Cited by
18References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 21, 1997 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | Feb 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of forming a packaged integrated circuit by aperturing a discrete packaging layer attached on a silicon substrate. A plurality of solder leads are formed on the layer. Electrical connections are formed from the leads to pads on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.