CMOS integrated circuit device and inspection method thereof
US6023186A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 24, 1998 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | Jul 24, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3004
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A CMOS integrated circuit device enabling accurate inspection of its static power source current includes: a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of the p-channel MOS transistor; a second pad connected to the source of the n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well having formed the p-channel MOS transistor; an n-type diffused region formed in the p-type substrate or p-well having formed the n-channel MOS transistor; a third pad connected through the p-type diffused region to the n-type substrate or n-well having formed the p-channel MOS transistor; and a fourth pad connected through the n-type diffused region to the p-type substrate or p-well having formed the n-channel MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.