Amplifier with reduced input capacitance
US6023194A · kind A · utility
5Cited by
9References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 23, 1997 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | May 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/513
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A JFET preamplifier for use with a high impedance transducer, having an inherently capacitive input bias impedance. The capacitance of the input bias impedance is effectively neutralized by capacitively coupling the JFET gate bias circuit to the source electrode of the JFET. The JFET preamplifier is configured as a source follower which reduces any capacitance between the JFET gate and source electrode by the open loop gain of the amplifier. By capacitively coupling the JFET gate bias circuit capacitance to the JFET source electrode, the overall input capacitance of the preamplifier stage is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.