Error estimation circuit and method for providing a read channel error signal
US6023383A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 1997 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | Mar 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B5/012
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A read channel (18) for use in a mass storage system is provided. The read channel (18) includes a plurality of circuit modules circuit and an error estimation circuit (50). The plurality of circuit modules may include circuitry such as a VGA (40), an LPF (42), and an equalizer (48), for conditioning an analog data signal. The plurality of circuit modules receive the analog data signal from a disk/head assembly (12) and condition the signal to generate a digital data signal. The error estimation circuit (50) receives an analog signal from one of the plurality of circuit modules, such as the equalizer (48), and analyzes the analog signal to generate an analog error output signal (94) that is used in the read channel (18) and provided to external circuitry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.