Method of achieving narrow V.sub.T distribution after erase in flash EEPROM
US6023426A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1998 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | Mar 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3404
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method of correcting overerased memory cells in a flash EEPROM memory cell after erase so as to produce a narrow threshold voltage distribution width. A ground potential is applied to all of the sources and substrates of the cells in the array of memory cells. First positive pulse voltages are simultaneously applied to each word line in a first timed sequence on a word line by word line basis. A second positive pulse voltage is simultaneously applied to each bit line in a second timed sequence in a bit line by bit line basis when the first positive pulse voltages are being applied to a first word line and is then repeated for each subsequent word line until a last word line is applied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.