Scoreboarding for DRAM access within a multi-array DRAM device using simultaneous activate and read/write accesses
US6023745A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 8, 1996 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | Aug 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0215
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for performing memory array/row scoreboarding in a dynamic access memory (DRAM) having dual bank access. The DRAM of the present invention allows dual simultaneous memory accesses into a memory divided into a plurality of arrays (e.g., 48 arrays). Each array of the DRAM contains a plurality of rows (e.g., 256). Each row of the DRAM contains storage for a certain amount of data bits (e.g., 1024). The DRAM in one configuration contains 1.5 Megabytes of memory. During a dual bank DRAM access, the system allows a first access for pre-opening a row (e.g., a page) of DRAM memory within a first array while simultaneously allowing a second access for reading/writing data to an opened row of another array aside from the first array. The present invention scoreboarding system tracks the rows that are currently open so that immediate read/write accesses can take place. Upon presentation of a row and array, the scoreboard determines if the presented row is currently open, and if so, generates a hit signal that allows an immediate read/write access to the presented row. If the presented row is not open, the present invention generates a miss signal so that the row can be …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.