Method and apparatus for utilizing mux scan flip-flops to test speed related defects by delaying an active to inactive transition of a scan mode signal

US6023778A · kind A · utility

Assignee

• Intel Corporation · US

Inventor

• Hehching Harry Li · Portland, US

Key dates

• Filing date: Dec 12, 1997
• Grant date: Feb 8, 2000
• Expiry date: Dec 12, 2017

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31858
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A method and an apparatus utilizing mux scan flip-flops to test for timing-related defects. In one embodiment, a delay circuit is used to act as a buffer for a scan enable signal received by the mux scan flip-flops of a test circuit. The scan mode signal is first sent to the delay circuit, which then distributes the scan mode signal to the mux scan flip-flops. Since each delay circuit can serve as the buffer for numerous mux scan flip-flops, the scan mode signal may be sent initially to a smaller number of delay circuits instead of the thousands of mux scan flip-flops that may be distributed throughout the entire integrated circuit. Furthermore, in one embodiment the delay circuit delays propagation of active-to-inactive transitions of the scan enable signal by one clock cycle, synchronizing the system clock cycle with the active-to-inactive transitions of the scan mode signal. In one embodiment, inactive-to-active transitions of the scan enable signal are propagated without the one clock cycle delay. With the present invention, the mux scan flip-flops may be loaded and unloaded with test data at slower scan clock speeds, and the integrated circuit may be operated at full system cl…