RAM based key equation solver apparatus
US6023782A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1996 |
| Grant date | Feb 8, 2000 |
| Priority date | — |
| Expiry date | Dec 13, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is a circuit for performing a computation of a plurality of coefficients of an error locator polynomial and a plurality of coefficients of an error evaluator polynomial in a system for correcting errors in a Reed-Solomon encoded datastream, comprising a syndrome generator outputting syndromes of the datastream. The circuit of the present invention is coupled to the syndrome generator and receives the syndromes. The present invention comprises an arithmetic unit iteratively generating intermediate and final values of the plurality of coefficients of an error locator polynomial and the plurality of coefficients of an error evaluator polynomial; a random access memory, storing the intermediate and final values of the plurality of coefficients of an error locator polynomial and the plurality of coefficients of an error evaluator polynomial; and a control unit, controlling the arithmetic unit and the memory and detecting when the computation of the plurality of coefficients of an error locator polynomial and the plurality of coefficients of an error evaluator polynomial has been completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.