Two-step etching process for forming self-aligned contacts
US6025255A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 1998 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Jun 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31116
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The practice of forming self-aligned contacts in MOSFETs using a silicon nitride gate sidewall and a silicon nitride gate cap has found wide acceptance, particularly in the manufacture of DRAMs, where bitline contacts are formed between two adjacent wordlines, each having a nitride sidewall. The contact etch requires a an RIE etch having a high oxide/nitride selectivity. Current etchants rely upon the formation of a polymer over nitride surfaces which enhances oxide/nitride selectivity. However, for contact widths of less than 0.35 microns, as are encountered in high density DRAMs, the amount of polymer formation required to attain a high selectivity causes the contact opening to close over with polymer before the opening is completely etched. This results in opens or unacceptably resistive contacts. On the other hand, if the etchant is adjusted to produce too little polymer, the nitride cap and sidewalls are thinned or etched through, producing gate to source/drain shorts. The invention describes a two step etching process whereby the contact opening is initially etched at high selectivity, and then, as the contact channel narrows, the polymer formation rate is reduced to prevent …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.