Programmable switch matrix and method of programming
US6025735A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1996 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Dec 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17756
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A switch network (22) in a Field Programmable Gate Array (FPGA) which operates as a combination of a programming transistor (34) and a ferroelectric transistor (32). The programming transistor (34) is selected to transfer a polarizing voltage to a gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an on-state. The ferroelectric transistor (32) functions as a nonvolatile latch and pass device to provide the electrical interconnect path that links multiple Configurable Logic Blocks (CLBs). The programming transistor (34) is selected to transfer a depolarizing voltage to the gate terminal of the ferroelectric transistor (32) for programming the ferroelectric transistor (32) in an off-state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.