Clock feeding circuit and method for adjusting clock skew
US6025740A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 3, 1993 |
| Grant date | Feb 15, 2000 |
| Priority date | — |
| Expiry date | Sep 3, 2013 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00323
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock feeding circuit for an integrated circuit includes logic circuit regions, a clock signal source, an input buffer connected to the source, and delay adjusting circuits. Each logic circuit region has a plurality of logic circuits, a buffer circuit for receiving the clock signal and providing it to the logic circuits, and interconnections wiring the logic circuits to the buffer circuit such that clock skew is minimized in the region. The adjusting circuits are disposed between the buffer and the respective logic circuit regions. Each adjusting circuit is composed of a plurality of delay elements, the number of which is pre-selected to determine the delay of the clock signal passing through it. A method for designing the integrated circuit includes (a) creating a schematic representation of the integrated circuit, (b) determining a layout and interconnections of each region, by which the clock skew in the regions is minimized among the logic circuits of each region, including simulating transmission of a clock signal from the clock source to each region to determine delays times of the clock signal from the clock source to the logic circuits; and (c) determining adjustments to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.